Date of Award

4-2018

Degree Name

Master of Science in Engineering

Department

Electrical and Computer Engineering

First Advisor

Dr. Fahad Saeed

Second Advisor

Bradley J. Bazuin, Ph.D.

Third Advisor

Lina Sawalha, Ph.D.

Keywords

Graph sampling, parallel computing, big data, OpenCL, Field Programmable Gate Array (FPGA)

Access Setting

Masters Thesis-Open Access

Abstract

Energy efficiency is a crucial problem in data centers where big data is generally represented by directed or undirected graphs. Analysis of this big data graph is challenging due to volume and velocity of the data as well as irregular memory access patterns. Graph sampling is one of the most effective ways to reduce the size of graph while maintaining crucial characteristics. This thesis presents design and implementation of a field programmable gate array (FPGA) based graph sampling method which is both time- and energy-efficient. This is in contrast to existing parallel approaches which include memory-distributed clusters, multicore and GPUs. Our strategy utilizes a novel graph data structure, that we call COPRA which allows time- and memory-efficient representation of graphs suitable for reconfigurable hardware such as FPGAs. Our experiments show that our proposed techniques are 2x faster and 3x more energy efficient as compared to serial CPU version of the algorithm. We further show that our proposed techniques give comparable speedups to graphical processing unit (GPU) and multi-threaded CPU architecture while energy consumption is 10x less than GPU and 2x less than CPU.

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