Author

Chansilp

Date of Award

4-2000

Degree Name

Master of Science in Engineering

Department

Electrical and Computer Engineering

First Advisor

Dr. Damon A. Miller

Second Advisor

Dr. Frank L. Severance

Third Advisor

Dr. Hossein Mousavineshad

Fourth Advisor

Dr. John Gesink

Access Setting

Masters Thesis-Open Access

Abstract

A chaotic oscillator may be used as the basic component of an associative memory (AM). An AM is capable of pattern separation and noise reduction. Chua's circuit is a widely used chaotic oscillator. This circuit consists of a nonlinear resistor, two capacitors, an inductor and a resistor. A discrete implementation of Chua's circuit may be built using operational amplifiers, resistors, diodes, or discrete bipolar transistors. CMOS integrated circuit technology provides the opportunity for a compact implementation which enables construction of systems requiring a large number of oscillators. This thesis develops an integrated circuit design based on previous work performed by Cruz et. al. (1993).

The IC chip has been designed using a 2 μ m CMOS process. The IC consists of four operational transconductance amplifiers (OTAs), a resistor and three capacitors. The first two OTAs operate as Chua's diode (Cruz 1993) and the other two OTAs in conjunction with the third capacitor realize an inductor. The design process initially used the Spice3f4 circuit simulation package. The final design used Mentor Graphics for simulation, physical layout, Design Rule Checks (DRC), Layout Versus Schematic checks (LVS) and parasitic extraction. All data files as required by fabrication via the MOSIS service were generated.

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