Author

Shanbhag

Date of Award

6-1994

Degree Name

Master of Science

Department

Computer Science

First Advisor

Dr. Naveed A. Sherwani

Second Advisor

Dr. Alfred Boals

Third Advisor

Dr. Ajay Gupta

Access Setting

Masters Thesis-Open Access

Abstract

Floorplanning is one of the important phases of the VLSI Physical Design cycle. The quality of a floorplan is usually not evident until the routing phase. A bad floorplan can lead to an unroutable design requiring another iteration of the floorplanning phase. Use of over-the-cell routing has led to zero routing footprints. Any further reduction in area of the layout is possible only by reducing the white space or the vacant space from the floorplan, that is by improving the floorplan of the layout.

Currently, the Mixed Block and Cell (MBC) design style is gaining popularity. This evolving design style is generally used to design high performance microprocessor chips. In the last three to four years, most of the microprocessors have been designed using this design style.

In this thesis, we develop a floorplanning scheme for Mixed Block and Cell designs which differs radically from all existing approaches. Existing algorithms, deal with rectangular shaped flexible blocks while generating the floorplans. In our algorithm, we exploit the flexibility of the standard cell regions by assigning rectilinear shapes to these regions. This improves not only the area of the layout but can also improve the performance of the design. We have developed an interactive tool, called "ARCHITECT" based on our algorithm, for floorplanning of MBC designs.

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