Martin Cowley

Date of Award


Degree Name

Master of Science


Electrical and Computer Engineering

First Advisor

Dr. Lina Sawalha

Second Advisor

Dr. Janos Grantner

Third Advisor

Dr. Bradley Bazuin


Dataflow, microarchitecture, ISA, sub-ISA

Access Setting

Masters Thesis-Open Access


Instruction set architectures (ISAs) such as x86, ARM, and RISC-V follow the control flow model of computation, where a program is defined as a sequence of instructions. Early processors executed instructions one-by-one based on the control flow of a program. Dataflow is an alternative model of computation that uses the availability of data to drive instruction execution. Any instruction can be chosen for execution, independent of the instruction order, as long as the data is available for that instruction. While modern processors incorporate concepts of the dataflow model in the microarchitecture, the implementation of the ISA, the amount of instruction level parallelism is still limited. Explicit dataflow architectures bring the concept of dataflow execution into the ISA. This increases the amount of parallelism, but also introduces problems, such as control flow bottlenecks, inefficient data structures, and lack of speculative execution, that have prevented dataflow architectures from surpassing Von Neumann for all applications. Rather than chose one model or the other, this work extends the RISC-V ISA with a dataflow sub-ISA. A microarchitecture implementation of this ISA is capable of executing both types of instructions: Von Neumann and dataflow. This thesis introduces a dataflow sub-ISA and determines when it is best to use the dataflow subset, and when the standard instructions give better performance. The ideal situations for dataflow are sections of code with simple control structures and irregular memory accesses. A program with regular memory accesses and simple control structures gave a speedup of 9% over the Von Neumann version, and a similar irregular application was estimated to have a speedup of 1.2x.