Date of Award
Master of Science
Electrical and Computer Engineering
Dr. E.S. Abuelvaman
Dr. S. H. Mousavinezhad
Dr. C.A. Davis
Masters Thesis-Open Access
The need for high speed addition is forcing digital system designers to trade off space. If speed is used as a criterion to judge adders, then the Ripple Carry Adder (RCA) and the Carry Look Ahead Adders (CLAAD) will rank last and first respectively. On the other hand, if space is used, then the order of these two is reversed. The rest of the adders rank between these two. This paper evaluates RCA, CLAAD, and some of the other well documented adders. Both space and speed are used to judge the merits of each of these, and whether or not they qualify as asynchronous adders. This process led to the design of a new, high speed asynchronous adder. Both probability theory and simulation are used to demonstrate the superiority of new design.
Shankarreddy, Poornima Y., "Evaluation and Implementation of Asynchronous Adders" (1993). Master's Theses. 824.