Date of Award
Master of Science
Dr. Naveed A. Sherwani
Dr. Alfred Boals
Dr. Ajay Gupta
Masters Thesis-Open Access
The clock signal is vital in maintaining proper dataflow, and thus the total throughput, of a high performance synchronous system.
In this thesis, we develop a clock distribution scheme for high performance systems which maximizes the operating clock frequency. We develop an algorithm which routes a planar clock tree with zero skew, minimum source to sink pathlength, and minimal total wirelength. The algorithm also provides a smooth tradeoff between maximum source to sink pathlength and total wirelength while keeping the clock skew at zero.
In many microprocessor designs, multi-phase clocks are used for improved system design. Routing a multiple clock is complicated because we need to minimize not only the clock skew within a clock but we also minimize cross skew between different clocks. In this thesis, we present a clock routing technique for routing two phase clock.
Khan, "On Clock Routing Techniques for VLSI Synchronous Systems" (1993). Master's Theses. 837.