Shih-Ming Li

Date of Award


Degree Name

Master of Science


Electrical and Computer Engineering

First Advisor

Dr. E. Abuelyaman

Second Advisor

Dr. H. Mousavinezhad

Third Advisor

Dr. D. Johnson

Access Setting

Masters Thesis-Open Access


The most commonly used model for fault analysis is called the "Stuck-At" model. With this model, a faulty gate input and/or output is modeled as Stuck-at-0 (s--a-0) or Stuck-at-1 (s-a-1). After a certain number of test vectors are applied to a network, the percentage fault coverage is computed. This computed value relates to the percentage of stuck-at faults detectable at the output. Various studies have been made to enhance the performance of fault simulators. In this paper, a modified parallel simulator MODPAR for combinational circuits is presented. A comparison of simulation results from MODPAR is made with that of SCIRTSS (Hill & Huey, 1977), which employs a parallel simulation algorithm. Simulation data indicate that MODPAR enjoys simulation time advantage.