Power-Efficient and Highly Scalable Parallel Graph Sampling using FPGAs

Authors

Usman Tariq, WMUFollow
Umer Cheema, Intel
Fahad Saeed, Western Michigan UniversityFollow

Publication Date

Fall 2017

Document Type

Technical Report

Abstract

Energy efficiency is a crucial problem in data centers where big data is generally represented by directed or undirected graphs. Analysis of this big data graph is challenging due to volume and velocity of the data as well as irregular memory access patterns. Graph sampling is one of the most effective ways to reduce the size of graph while maintaining crucial characteristics. In this paper we present design and implementation of an FPGA based graph sampling method which is both time- and energy-efficient. This is in contrast to existing parallel approaches which include memory-distributed clusters, multicore and GPUs. Our strategy utilizes a novel graph data structure, that we call COPRA that allows time- and memory-efficient representation of graphs suitable for reconfigurable hardware such as FPGAs. Our experiments show that our proposed techniques are 2x faster and 3x more energy efficient as compared to serial CPU version of the algorithm. We further show that our proposed techniques give comparable speedups to GPU and multi-threaded CPU architecture while energy consumption is 10x less than GPU and 2x less than CPU.

Published Citation

Usman Tariq, Umer Cheema, and Fahad Saeed, "Power-Efficient and Highly Scalable Parallel Graph Sampling using FPGAs", In proceedings of International Conference on Reconfigurable Computing and FPGAs (ReConFig 2017), Mexico