Date of Award

4-2019

Degree Name

Doctor of Philosophy

Department

Electrical and Computer Engineering

First Advisor

Dr. Janos L. Grantner

Second Advisor

Dr. Ikhlas Abdel-Qader

Third Advisor

Dr. Azim Houshyar

Keywords

hardware accelerator, fuzzy-logic based image processing, FPGAs, SoCs

Abstract

Rapid development in the architecture and fabrication technology of field programmable gate array (FPGA) and system on a chip (SoC) in the last two decades is dramatically increasing the reliability of those devices as a cost-effective alternative for traditional real-time image processing systems. Module reusability nature of FPGA and SoC development decreases design and implementation time noticeably. On-site reconfigurability allows for intensive design alterations to occur at a small cost. This study is presenting the design and implementation of a new hardware accelerator for an edge detector on Xilinx 7 series FPGA devices based on a fuzzy logic approach. The fuzzy system comprises four fuzzy inputs and an inference system with seven rules implementing the knowledge base, and a single crisp output represents the intensity level of a pixel in the output image. The pipelined hardware accelerator consists of seven stages, each of which is operating at one clock cycle on a frequency range between 83-125 MHz depending on the speed grade of the chip that was used by design. The performance of the fuzzy logic system is compared to other edge detection methods and shows a big advantage. The hardware accelerator is outperforming its software counterpart by a factor of ten thousand times.

This study also presents a hardware/software co-design of a reconfigurable support platform for a fuzzy logic-based spatial image processing filter using Xilinx all programmable SoC (AP SoC). The hardware accelerator mentioned in the first part is deployed to the programmable logic (PL) part of the device, with additional hardware to control the data exchange between the hardware accelerator and the main memory on the programmable system (PS) part of the chip where the input and output images are buffered. Different design aspects were tested and tuned, such as the device utilization, the burst length memory transactions, the size of local buffers, and the PL fabric clock frequency.

The system performance was assessed using multiple configurations. Using a system design consisting of a single instance of the support platform along with a hardware accelerator, the system processed a test frame of 1920x1080 pixels in 19.435 milliseconds, resulting in a processing rate of approximately 50 frames per second. In another configuration, four support platforms and their respective hardware accelerator deployed to the PL fabric of the AP SoC device, and the processing rate was 205 frames per second.

Access Setting

Dissertation-Open Access

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