Date of Award

12-2015

Degree Name

Master of Science in Engineering

Department

Electrical and Computer Engineering

First Advisor

Dr. Bradley J. Bazuin

Second Advisor

Dr. Janos L. Grantner

Third Advisor

Dr. Lina Sawalha

Keywords

SDR, DDC-USRP, Curdic Processor, CIC filter decimator, FPGA pattern generator

Access Setting

Masters Thesis-Open Access

Abstract

Modern communication systems have increasingly attempted to trade off the digital signal processing for analog circuitry. In performing this tradeoff, advanced algorithms have been implemented in both custom programmable hardware and in software; such systems are commonly called Software Defined Radios (SDR). Advanced software defined radios consist of highly configurable hardware and computers used as digital signal processing (DSP) platforms that provide the technology for realizing current and future generations of digital wireless communication infrastructure. Many sophisticated signal processing tasks are performed in SDR, including compression algorithms, channel estimation, equalization, forward error correction and protocol management. This research has focused on the custom and programmable hardware DSP devices which are commonly found prior to the baseband processor, performing critical tasks appearing after the analog to digital converter. The DSP techniques that are involved in this research are tuning, filtering and decimation of a received communication signal.

The research activity performed the fixed-point algorithmic simulation in MATLAB and the Xilinx VHDL implementation of integer precision complex mixing, high rate filter decimation and two stage lower rate half-band filter decimation in order to develop a communication signal processor. In addition, a Xilinx based digital test data generator and output comparator design was developed to provide test data and analyze results in real time for the Xilinx communication signal processor developed.

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